The capabilities of mobile communication devices continue to expand. For example, FM (frequency modulation) radio is now available in almost all mobile telephones, personal data assistants, and other suitable devices, allowing users to listen to FM radio broadcasts on their mobile communication devices.
Peripherals like FM radio in mobile communication devices may have very special requirements in terms of reference frequencies. For example, in a “radio only” mode, the high reference frequencies are typically not active to save power, which requires the FM radio to work with a relatively low frequency real time clock (e.g. 32.768 kHz). Alternately, in a “normal” mode, the FM radio is required to work with a high frequency reference (e.g. 26 MHz). This vast range of operational frequencies places considerable challenges on frequency synthesis, including handling the phase noise requirements, the area of a possible integrated loop-filter, and possible requirements on FM transmit functionality with high signal-to-noise ratio (SNR).
Conventional methods of frequency synthesis, such as integer-N phase-locked loop (PLL), software defined phase-locked loop (SDPLL), and frequency-locked loop (FLL), may be used for frequency synthesis depending, for example, on operating circumstances or device design. These alternatives may suffer from drawbacks, however, due to relatively large size (or area) needed for integration due to the requirements for reducing phase noise, particularly for the low reference frequency in the audio bands.